Scott, “An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size,” 1989 Int. Yamazaki, “A 6ns 4Mb ECL I/O BiCMOS SRAM with LV TTL Mask Option,” 1992 Int. Hotta, “CMOS/Bipolar Circuits for 60MHz Digital Processing,” 1986 Int. Rahim, “Second Generation BiCMOS Gate Array Technology,” 1987 Bipolar Circuits and Technology Meeting, pp. Uchida, “An 8ns 256K BiCMOS SRAM,” 1988 Int. Tuntasood, “Advanced 111 BiCMOS Technology for High Speed 256K SRAMs,” 1987 Symp. Kohyama, “A 1.01.um N-Well CMOS/ Bipolar Technology For VLSI Circuits”, 1984 Int. Nishio, “Performance and Structures of Scaled-Down Bipolar Devices Merged with CMOSFETs,” Int. Gallager, “Single Chip Carries Three Technologies,” Electronics Week, Dec. Pifer “, New High Voltage IC Technology”, 1984 Int. Alvarez, “Power BiCMOS - A Versatile IC Technology for Switching and Regulation Applications”, 1984 Custom Integrated Circuits Conference, pp. Gettemeyer, “Lateral DMOS Transistor Optimized for High Voltage BiCMOS Applications,” 1983 Int. Fay, “Mixed Process Puts High Power Under Control,” Electronic Design, Vol. Peppenger, “Single-Chip Linear Regulator Handles 125V I/O Differential,” Electronic Design, Sept. Davis, “Simplified Driver, New Applications Spur Plasma-Panel Usage,” Electronic Design News, Sept. Meindl, “A Monolithic 200-V CMOS Analog Switch,” J. Keller, “CMOS-Bipolar Monolithic Integrated Circuit Technology,” 1973 Int. Kwong, “Complementary MOS-Bipolar Transistor Structure,” IEEE Trans. Schucker, “BiCMOS Technology for Semi-Custom Integrated Circuits,” Cust. Tien, “2 µm Merged BIMOS Technology,” 1984 Int. This process is experimental and the keywords may be updated as the learning algorithm improves.Ī.R. These keywords were added by machine and not by the authors. The inherent robustness of BiCMOS with respect to temperature and process variations also reduces the variability of final electrical parameters, resulting in a higher percentage of prime units, an important economic consideration. Compared to CMOS, BiCMOS’s reduced dependence on capacitive load and the multiple circuit and I/Os configurations possible greatly enhance design flexibility and can lead to reduced design cycle time.

It follows that BiCMOS technology offers the advantages of: 1) improved speed over CMOS, 2) lower power dissipation than Bipolar (simplifying packaging and board requirements), 3) flexible I/Os (TTL, CMOS, or ECL), 4) high performance analog, and 5) latchup immunity.

This last point is especially significant given the growing importance package limitations in high speed systems. Bipolar technology has advantages over CMOS in switching speed, current drive per unit area, noise performance, analog capability, and I/O speed. CMOS technology maintains an advantage over Bipolar in power dissipation, noise margins, packing density, and the ability to integrate large complex functions with high yields. By retaining the benefits of Bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually. BiCMOS technology combines Bipolar and CMOS transistors in a single integrated circuit.

Bipolar transistor inverter